serial.c File Reference

#include "devices/serial.h"
#include <debug.h>
#include "devices/input.h"
#include "devices/intq.h"
#include "devices/timer.h"
#include "threads/io.h"
#include "threads/interrupt.h"
#include "threads/synch.h"
#include "threads/thread.h"

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Macros
#define	IO_BASE   0x3f8
#define	RBR_REG   (IO_BASE + 0) /* Receiver Buffer Reg. (read-only). */
#define	THR_REG   (IO_BASE + 0) /* Transmitter Holding Reg. (write-only). */
#define	IER_REG   (IO_BASE + 1) /* Interrupt Enable Reg.. */
#define	LS_REG   (IO_BASE + 0) /* Divisor Latch (LSB). */
#define	MS_REG   (IO_BASE + 1) /* Divisor Latch (MSB). */
#define	IIR_REG   (IO_BASE + 2) /* Interrupt Identification Reg. (read-only) */
#define	FCR_REG   (IO_BASE + 2) /* FIFO Control Reg. (write-only). */
#define	LCR_REG   (IO_BASE + 3) /* Line Control Register. */
#define	MCR_REG   (IO_BASE + 4) /* MODEM Control Register. */
#define	LSR_REG   (IO_BASE + 5) /* Line Status Register (read-only). */
#define	IER_RECV   0x01 /* Interrupt when data received. */
#define	IER_XMIT   0x02 /* Interrupt when transmit finishes. */
#define	LCR_N81   0x03 /* No parity, 8 data bits, 1 stop bit. */
#define	LCR_DLAB   0x80 /* Divisor Latch Access Bit (DLAB). */
#define	MCR_OUT2   0x08 /* Output line 2. */
#define	LSR_DR   0x01 /* Data Ready: received data byte is in RBR. */
#define	LSR_THRE   0x20 /* THR Empty. */

Enumerations
enum	{ UNINIT , POLL , QUEUE }

Functions
static void	set_serial (int bps)
static void	putc_poll (uint8_t)
static void	write_ier (void)
static void	init_poll (void)
void	serial_init_queue (void)
void	serial_putc (uint8_t byte)
void	serial_flush (void)
void	serial_notify (void)
static void	serial_interrupt (struct intr_frame *f UNUSED)

Variables
static enum { ... }	mode
static struct intq	txq
static intr_handler_func	serial_interrupt

Macro Definition Documentation

FCR_REG

#define FCR_REG   (IO_BASE + 2) /* FIFO Control Reg. (write-only). */

IER_RECV

#define IER_RECV   0x01 /* Interrupt when data received. */

IER_REG

#define IER_REG   (IO_BASE + 1) /* Interrupt Enable Reg.. */

IER_XMIT

#define IER_XMIT   0x02 /* Interrupt when transmit finishes. */

IIR_REG

#define IIR_REG   (IO_BASE + 2) /* Interrupt Identification Reg. (read-only) */

IO_BASE

#define IO_BASE   0x3f8

LCR_DLAB

#define LCR_DLAB   0x80 /* Divisor Latch Access Bit (DLAB). */

LCR_N81

#define LCR_N81   0x03 /* No parity, 8 data bits, 1 stop bit. */

LCR_REG

#define LCR_REG   (IO_BASE + 3) /* Line Control Register. */

LS_REG

#define LS_REG   (IO_BASE + 0) /* Divisor Latch (LSB). */

LSR_DR

#define LSR_DR   0x01 /* Data Ready: received data byte is in RBR. */

LSR_REG

#define LSR_REG   (IO_BASE + 5) /* Line Status Register (read-only). */

LSR_THRE

#define LSR_THRE   0x20 /* THR Empty. */

MCR_OUT2

#define MCR_OUT2   0x08 /* Output line 2. */

MCR_REG

#define MCR_REG   (IO_BASE + 4) /* MODEM Control Register. */

MS_REG

#define MS_REG   (IO_BASE + 1) /* Divisor Latch (MSB). */

RBR_REG

#define RBR_REG   (IO_BASE + 0) /* Receiver Buffer Reg. (read-only). */

THR_REG

#define THR_REG   (IO_BASE + 0) /* Transmitter Holding Reg. (write-only). */

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
UNINIT
POLL
QUEUE

{ UNINIT, POLL, QUEUE } mode;

Function Documentation

init_poll()

static void init_poll ( void  )

static

                 {
    ASSERT (mode == UNINIT);
    outb (IER_REG, 0);                    /* Turn off all interrupts. */
    outb (FCR_REG, 0);                    /* Disable FIFO. */
    set_serial (115200);                  /* 115.2 kbps, N-8-1. */
    outb (MCR_REG, MCR_OUT2);             /* Required to enable interrupts. */
    intq_init (&txq);
    mode = POLL;
}

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putc_poll()

static void putc_poll ( uint8_t  byte )

static

                         {
    ASSERT (intr_get_level () == INTR_OFF);
 
    while ((inb (LSR_REG) & LSR_THRE) == 0)
        continue;
    outb (THR_REG, byte);
}

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serial_flush()

void serial_flush

(

void

)

                    {
    enum intr_level old_level = intr_disable ();
    while (!intq_empty (&txq))
        putc_poll (intq_getc (&txq));
    intr_set_level (old_level);
}

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serial_init_queue()

void serial_init_queue

(

void

)

                         {
    enum intr_level old_level;
 
    if (mode == UNINIT)
        init_poll ();
    ASSERT (mode == POLL);
 
    intr_register_ext (0x20 + 4, serial_interrupt, "serial");
    mode = QUEUE;
    old_level = intr_disable ();
    write_ier ();
    intr_set_level (old_level);
}

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serial_interrupt()

static void serial_interrupt ( struct intr_frame *f  UNUSED )

static

                                               {
    /* Inquire about interrupt in UART.  Without this, we can
       occasionally miss an interrupt running under QEMU. */
    inb (IIR_REG);
 
    /* As long as we have room to receive a byte, and the hardware
       has a byte for us, receive a byte.  */
    while (!input_full () && (inb (LSR_REG) & LSR_DR) != 0)
        input_putc (inb (RBR_REG));
 
    /* As long as we have a byte to transmit, and the hardware is
       ready to accept a byte for transmission, transmit a byte. */
    while (!intq_empty (&txq) && (inb (LSR_REG) & LSR_THRE) != 0)
        outb (THR_REG, intq_getc (&txq));
 
    /* Update interrupt enable register based on queue status. */
    write_ier ();
}

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serial_notify()

void serial_notify

(

void

)

                     {
    ASSERT (intr_get_level () == INTR_OFF);
    if (mode == QUEUE)
        write_ier ();
}

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serial_putc()

void serial_putc

(

uint8_t

byte

)

                           {
    enum intr_level old_level = intr_disable ();
 
    if (mode != QUEUE) {
        /* If we're not set up for interrupt-driven I/O yet,
           use dumb polling to transmit a byte. */
        if (mode == UNINIT)
            init_poll ();
        putc_poll (byte);
    } else {
        /* Otherwise, queue a byte and update the interrupt enable
           register. */
        if (old_level == INTR_OFF && intq_full (&txq)) {
            /* Interrupts are off and the transmit queue is full.
               If we wanted to wait for the queue to empty,
               we'd have to reenable interrupts.
               That's impolite, so we'll send a character via
               polling instead. */
            putc_poll (intq_getc (&txq));
        }
 
        intq_putc (&txq, byte);
        write_ier ();
    }
 
    intr_set_level (old_level);
}

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set_serial()

static void set_serial ( int  bps )

static

                     {
    int base_rate = 1843200 / 16;         /* Base rate of 16550A, in Hz. */
    uint16_t divisor = base_rate / bps;   /* Clock rate divisor. */
 
    ASSERT (bps >= 300 && bps <= 115200);
 
    /* Enable DLAB. */
    outb (LCR_REG, LCR_N81 | LCR_DLAB);
 
    /* Set data rate. */
    outb (LS_REG, divisor & 0xff);
    outb (MS_REG, divisor >> 8);
 
    /* Reset DLAB. */
    outb (LCR_REG, LCR_N81);
}

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write_ier()

static void write_ier ( void  )

static

                 {
    uint8_t ier = 0;
 
    ASSERT (intr_get_level () == INTR_OFF);
 
    /* Enable transmit interrupt if we have any characters to
       transmit. */
    if (!intq_empty (&txq))
        ier |= IER_XMIT;
 
    /* Enable receive interrupt if we have room to store any
       characters we receive. */
    if (!input_full ())
        ier |= IER_RECV;
 
    outb (IER_REG, ier);
}

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Variable Documentation

enum { ... } mode

serial_interrupt

intr_handler_func serial_interrupt

static

txq

struct intq txq

static