interrupt.c File Reference

#include "threads/interrupt.h"
#include <debug.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdio.h>
#include "threads/flags.h"
#include "threads/intr-stubs.h"
#include "threads/io.h"
#include "threads/thread.h"
#include "threads/mmu.h"
#include "threads/vaddr.h"
#include "devices/timer.h"
#include "intrinsic.h"

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Classes
struct	gate

Macros
#define	INTR_CNT   256
#define	make_gate(g, function, d, t)
#define	make_intr_gate(g, function, dpl)   make_gate((g), (function), (dpl), 14)
#define	make_trap_gate(g, function, dpl)   make_gate((g), (function), (dpl), 15)

Functions
static void	pic_init (void)
static void	pic_end_of_interrupt (int irq)
void	intr_handler (struct intr_frame *args)
enum intr_level	intr_get_level (void)
enum intr_level	intr_set_level (enum intr_level level)
enum intr_level	intr_enable (void)
enum intr_level	intr_disable (void)
void	intr_init (void)
static void	register_handler (uint8_t vec_no, int dpl, enum intr_level level, intr_handler_func *handler, const char *name)
void	intr_register_ext (uint8_t vec_no, intr_handler_func *handler, const char *name)
void	intr_register_int (uint8_t vec_no, int dpl, enum intr_level level, intr_handler_func *handler, const char *name)
bool	intr_context (void)
void	intr_yield_on_return (void)
void	intr_dump_frame (const struct intr_frame *f)
const char *	intr_name (uint8_t vec)

Variables
static struct gate	idt [INTR_CNT]
static struct desc_ptr	idt_desc
static intr_handler_func *	intr_handlers [INTR_CNT]
static const char *	intr_names [INTR_CNT]
static bool	in_external_intr
static bool	yield_on_return

Macro Definition Documentation

INTR_CNT

#define INTR_CNT   256

make_gate

#define make_gate	(		g,
			function,
			d,
			t
	)

Value:

{ \
    ASSERT ((function) != NULL); \
    ASSERT ((d) >= 0 && (d) <= 3); \
    ASSERT ((t) >= 0 && (t) <= 15); \
    *(g) = (struct gate) { \
        .off_15_0 = (uint64_t) (function) & 0xffff, \
        .ss = SEL_KCSEG, \
        .ist = 0, \
        .rsv1 = 0, \
        .type = (t), \
        .s = 0, \
        .dpl = (d), \
        .p = 1, \
        .off_31_16 = ((uint64_t) (function) >> 16) & 0xffff, \
        .off_32_63 = ((uint64_t) (function) >> 32) & 0xffffffff, \
        .rsv2 = 0, \
    }; \
}

make_intr_gate

#define make_intr_gate	(		g,
			function,
			dpl
	)		make_gate((g), (function), (dpl), 14)

make_trap_gate

#define make_trap_gate	(		g,
			function,
			dpl
	)		make_gate((g), (function), (dpl), 15)

Function Documentation

intr_context()

bool intr_context

(

void

)

                    {
    return in_external_intr;
}

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intr_disable()

enum intr_level intr_disable

(

void

)

                    {
    enum intr_level old_level = intr_get_level ();
 
    /* Disable interrupts by clearing the interrupt flag.
       See [IA32-v2b] "CLI" and [IA32-v3a] 5.8.1 "Masking Maskable
       Hardware Interrupts". */
    asm volatile ("cli" : : : "memory");
 
    return old_level;
}

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intr_dump_frame()

void intr_dump_frame

(

const struct intr_frame *

f

)

                                             {
    /* CR2 is the linear address of the last page fault.
       See [IA32-v2a] "MOV--Move to/from Control Registers" and
       [IA32-v3a] 5.14 "Interrupt 14--Page Fault Exception
       (#PF)". */
    uint64_t cr2 = rcr2();
    printf ("Interrupt %#04llx (%s) at rip=%llx\n",
            f->vec_no, intr_names[f->vec_no], f->rip);
    printf (" cr2=%016llx error=%16llx\n", cr2, f->error_code);
    printf ("rax %016llx rbx %016llx rcx %016llx rdx %016llx\n",
            f->R.rax, f->R.rbx, f->R.rcx, f->R.rdx);
    printf ("rsp %016llx rbp %016llx rsi %016llx rdi %016llx\n",
            f->rsp, f->R.rbp, f->R.rsi, f->R.rdi);
    printf ("rip %016llx r8 %016llx  r9 %016llx r10 %016llx\n",
            f->rip, f->R.r8, f->R.r9, f->R.r10);
    printf ("r11 %016llx r12 %016llx r13 %016llx r14 %016llx\n",
            f->R.r11, f->R.r12, f->R.r13, f->R.r14);
    printf ("r15 %016llx rflags %08llx\n", f->R.r15, f->eflags);
    printf ("es: %04x ds: %04x cs: %04x ss: %04x\n",
            f->es, f->ds, f->cs, f->ss);
}

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intr_enable()

enum intr_level intr_enable

(

void

)

                   {
    enum intr_level old_level = intr_get_level ();
    ASSERT (!intr_context ());
 
    /* Enable interrupts by setting the interrupt flag.
 
       See [IA32-v2b] "STI" and [IA32-v3a] 5.8.1 "Masking Maskable
       Hardware Interrupts". */
    asm volatile ("sti");
 
    return old_level;
}

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intr_get_level()

enum intr_level intr_get_level

(

void

)

                      {
    uint64_t flags;
 
    /* Push the flags register on the processor stack, then pop the
       value off the stack into `flags'.  See [IA32-v2b] "PUSHF"
       and "POP" and [IA32-v3a] 5.8.1 "Masking Maskable Hardware
       Interrupts". */
    asm volatile ("pushfq; popq %0" : "=g" (flags));
 
    return flags & FLAG_IF ? INTR_ON : INTR_OFF;
}

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intr_handler()

void intr_handler

(

struct intr_frame *

args

)

                                        {
    bool external;
    intr_handler_func *handler;
 
    /* External interrupts are special.
       We only handle one at a time (so interrupts must be off)
       and they need to be acknowledged on the PIC (see below).
       An external interrupt handler cannot sleep. */
    external = frame->vec_no >= 0x20 && frame->vec_no < 0x30;
    if (external) {
        ASSERT (intr_get_level () == INTR_OFF);
        ASSERT (!intr_context ());
 
        in_external_intr = true;
        yield_on_return = false;
    }
 
    /* Invoke the interrupt's handler. */
    handler = intr_handlers[frame->vec_no];
    if (handler != NULL)
        handler (frame);
    else if (frame->vec_no == 0x27 || frame->vec_no == 0x2f) {
        /* There is no handler, but this interrupt can trigger
           spuriously due to a hardware fault or hardware race
           condition.  Ignore it. */
    } else {
        /* No handler and not spurious.  Invoke the unexpected
           interrupt handler. */
        intr_dump_frame (frame);
        PANIC ("Unexpected interrupt");
    }
 
    /* Complete the processing of an external interrupt. */
    if (external) {
        ASSERT (intr_get_level () == INTR_OFF);
        ASSERT (intr_context ());
 
        in_external_intr = false;
        pic_end_of_interrupt (frame->vec_no);
 
        if (yield_on_return)
            thread_yield ();
    }
}

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intr_init()

void intr_init

(

void

)

                 {
    int i;
 
    /* Initialize interrupt controller. */
    pic_init ();
 
    /* Initialize IDT. */
    for (i = 0; i < INTR_CNT; i++) {
        make_intr_gate(&idt[i], intr_stubs[i], 0);
        intr_names[i] = "unknown";
    }
 
#ifdef USERPROG
    /* Load TSS. */
    ltr (SEL_TSS);
#endif
 
    /* Load IDT register. */
    lidt(&idt_desc);
 
    /* Initialize intr_names. */
    intr_names[0] = "#DE Divide Error";
    intr_names[1] = "#DB Debug Exception";
    intr_names[2] = "NMI Interrupt";
    intr_names[3] = "#BP Breakpoint Exception";
    intr_names[4] = "#OF Overflow Exception";
    intr_names[5] = "#BR BOUND Range Exceeded Exception";
    intr_names[6] = "#UD Invalid Opcode Exception";
    intr_names[7] = "#NM Device Not Available Exception";
    intr_names[8] = "#DF Double Fault Exception";
    intr_names[9] = "Coprocessor Segment Overrun";
    intr_names[10] = "#TS Invalid TSS Exception";
    intr_names[11] = "#NP Segment Not Present";
    intr_names[12] = "#SS Stack Fault Exception";
    intr_names[13] = "#GP General Protection Exception";
    intr_names[14] = "#PF Page-Fault Exception";
    intr_names[16] = "#MF x87 FPU Floating-Point Error";
    intr_names[17] = "#AC Alignment Check Exception";
    intr_names[18] = "#MC Machine-Check Exception";
    intr_names[19] = "#XF SIMD Floating-Point Exception";
}

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intr_name()

const char * intr_name

(

uint8_t

vec

)

                        {
    return intr_names[vec];
}

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intr_register_ext()

void intr_register_ext	(	uint8_t	vec_no,
		intr_handler_func *	handler,
		const char *	name
	)

                          {
    ASSERT (vec_no >= 0x20 && vec_no <= 0x2f);
    register_handler (vec_no, 0, INTR_OFF, handler, name);
}

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intr_register_int()

void intr_register_int	(	uint8_t	vec_no,
		int	dpl,
		enum intr_level	level,
		intr_handler_func *	handler,
		const char *	name
	)

{
    ASSERT (vec_no < 0x20 || vec_no > 0x2f);
    register_handler (vec_no, dpl, level, handler, name);
}

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intr_set_level()

enum intr_level intr_set_level

(

enum intr_level

level

)

                                       {
    return level == INTR_ON ? intr_enable () : intr_disable ();
}

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intr_yield_on_return()

void intr_yield_on_return

(

void

)

                            {
    ASSERT (intr_context ());
    yield_on_return = true;
}

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pic_end_of_interrupt()

static void pic_end_of_interrupt ( int  irq )

static

                               {
    ASSERT (irq >= 0x20 && irq < 0x30);
 
    /* Acknowledge master PIC. */
    outb (0x20, 0x20);
 
    /* Acknowledge slave PIC if this is a slave interrupt. */
    if (irq >= 0x28)
        outb (0xa0, 0x20);
}

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pic_init()

static void pic_init ( void  )

static

                {
    /* Mask all interrupts on both PICs. */
    outb (0x21, 0xff);
    outb (0xa1, 0xff);
 
    /* Initialize master. */
    outb (0x20, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
    outb (0x21, 0x20); /* ICW2: line IR0...7 -> irq 0x20...0x27. */
    outb (0x21, 0x04); /* ICW3: slave PIC on line IR2. */
    outb (0x21, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
 
    /* Initialize slave. */
    outb (0xa0, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
    outb (0xa1, 0x28); /* ICW2: line IR0...7 -> irq 0x28...0x2f. */
    outb (0xa1, 0x02); /* ICW3: slave ID is 2. */
    outb (0xa1, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
 
    /* Unmask all interrupts. */
    outb (0x21, 0x00);
    outb (0xa1, 0x00);
}

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register_handler()

static void register_handler ( uint8_t  vec_no, int  dpl, enum intr_level  level, intr_handler_func *  handler, const char *  name  )

static

                                                      {
    ASSERT (intr_handlers[vec_no] == NULL);
    if (level == INTR_ON) {
        make_trap_gate(&idt[vec_no], intr_stubs[vec_no], dpl);
    }
    else {
        make_intr_gate(&idt[vec_no], intr_stubs[vec_no], dpl);
    }
    intr_handlers[vec_no] = handler;
    intr_names[vec_no] = name;
}

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Variable Documentation

idt

struct gate idt[INTR_CNT]

static

idt_desc

struct desc_ptr idt_desc

static

Initial value:

= {
    .size = sizeof(idt) - 1,
    .address = (uint64_t) idt
}

in_external_intr

bool in_external_intr

static

intr_handlers

intr_handler_func* intr_handlers[INTR_CNT]

static

intr_names

const char* intr_names[INTR_CNT]

static

yield_on_return

bool yield_on_return

static